The present invention concerns the testing of electronics systems, and specifically relates to testing interconnections among system components which may vary from one system to another, and from time to time within a single system.
Many electronics systems are constructed as a number of components or subassemblies electrically coupled together by socketed cables, backplane buses, or other means which allow the components to be moved, added, and replaced within the system. Digital computers in particular typically comprise a number of cards, boards, or books which perform major functions of the system, and which plug into a number of bus slots whose sockets contain signal buses, power distribution, and other wiring for connecting the functional cards to each other. Individual cards for a computer system often include several types of processor, different sizes of memory, and a large number of general and specialized input/output adapters for external storage devices, display terminals, and so forth. Many cards of a single type also commonly have in different models and engineering-change levels.
A computer or other system of this type may be easily customized to hundreds or thousands of different configurations to meet the needs of different users and to upgrade capabilities. But this flexibility has its disadvantages as well. Connectors such as those used between major system components are among the most failure-prone of electrical elements. Cables, wiring harnesses, and even printed-circuit wiring are also among the least reliable elements in modern electronics systems, and are often subject to mechanical stresses, environmental deterioration, and other wear mechanisms to a greater extent than other electrical elements.
Techniques exist for testing the smaller parts of complex systems, such as integrated circuits, modules, and even printed-circuit cards and other subsystems. One group of techniques in particular has been employed for a long time for testing integrated circuits. Called "level-sensitive scan design" (LSSD), "boundary scanning", and "STUMPS", these techniques employ banks of digital registers to store nominal data signals during operation of the system. In a selectable test mode, however, the register banks are electrically switched to form a single very long shift register. Test equipment shifts a string of bits forming a test vector into this chain of registers. Special clock signals apply these bits to inputs of the logic circuits or nets on the chip, and then receive the response bits output from the nets. This result vector is then shifted back into the test equipment for comparison with a vector of expected result bits.
These and similar techniques have been expanded to test larger components and subassemblies, such as multi-chip modules and even entire printed-circuit cards. But tests of the more failure-prone parts of large systems, the system interconnects between major components, has heretofore not been practical. The testing of entire systems is still practical only at the manufacturing stage, and even then requires expensive specialized test equipment. Many systems cannot be fully tested in the field during normal operation, or when a customer or service representative modifies them.
Conventional boundary scanning and similar test methodologies are not feasible for testing overall system interconnections, because such interconnections vary from one system to another and over time within a single System. These methodologies require advance knowledge of the wiring topology of the system in order to produce the correct test vectors and comparison data for the result vectors. Although it is theoretically possible to store data for every potential system configuration, even a relatively small midrange computer has hundreds or thousands of possible configurations, which would require impractically large amounts of storage. Also, of course, the system or test equipment would have to be able to determine in some way which of these myriad configurations actually exists in the system at the time the test is performed.
At the present time, then, there is no practical way to test the variable system-level interconnections among major components of a system which allows such components to be added, changed, and removed.